1. Field of the Invention
The present invention relates to a static semiconductor memory device, and more particularly, it relates to a structure for reducing power consumption, a chip occupied area and an access time in the static semiconductor memory device.
2. Description of the Prior Art
FIG. 28 schematically illustrates the overall structure of a conventional static semiconductor memory device. This figure illustrates the overall structure of an exemplary static semiconductor memory device of a 1-bit word structure for inputting/outputting 1-bit data DQ.
Referring to FIG. 28, the static semiconductor memory device includes a memory array 100 having a plurality of static memory cells arranged in rows and columns. This memory array 100, the internal structure of which is described later in detail, includes a plurality of word lines arranged in correspondence to the respective rows of the memory cells and connected with the memory cells of the corresponding rows respectively, and a plurality of bit line pairs arranged in correspondence to the respective columns of the memory cells and connected with the memory cells of the corresponding columns respectively. The memory array 100 is split into a plurality of memory blocks 101a, 101b, 101c and 101d sharing the rows (word lines) along the row direction.
In order to select any memory cell in this memory array 100, the static semiconductor memory device further includes an X address buffer 102 for receiving X address signal bits AX0 to AXm specifying a row of the memory array 100, a Y address buffer 103 for receiving Y address signal bits AY0 to AYn specifying the columns in the memory blocks 101a to 101d respectively, a Z address buffer 104 for receiving Z address signal bits AZ0 and AZ1 specifying one of the memory blocks 101a to 101d, an X decoder 105 for decoding an internal address signal from the X address buffer 102 and selecting a row in the memory array 100, a Y decoder 106 for decoding an internal address signal from the Y address buffer 103 and selecting a column in each of the memory blocks 101a to 101d, and a block selector 107 for receiving an internal address signal from the Z address buffer 104 and generating a block selection signal for specifying one of the memory blocks 101a to 101d.
The X address buffer 102 includes buffer circuits XB0 to XBm provided in correspondence to the X address signal bits AX0 to AXm respectively for receiving the corresponding address signal bits AX0 to AXm and generating complementary internal address signal bits. The Y address buffer 103 includes buffer circuits YB0 to YBn provided in correspondence to the Y address signal bits AY0 to AYn respectively for receiving the corresponding address signal bits AY0 to AYn and generating complementary internal address signal bits. The Z address buffer 104 includes buffer circuits ZB0 and ZB1 provided in correspondence to the address signal bits AZ0 and AZ1 respectively for receiving the corresponding address signal bits AZ0 and AZ1 and generating complementary internal address signal bits.
The static semiconductor memory device further includes sense amplifiers 110a, 110b, 110c and 110d provided in correspondence to the memory blocks 101a to 101d respectively for amplifying data of selected memory cells of the corresponding memory blocks 101a to 101d respectively for transmission onto a common data bus 112 when activated, and write drivers 111a to 111d for amplifying the data on the common data bus 112 for writing in the selected memory cells of the corresponding memory blocks 101a to 101d respectively when activated. One of the sense amplifiers 110a to 110d is selectively driven into an active state in response to the block selection signal from the block selector 107 in a data write operation. Only the sense amplifier or the write driver provided in correspondence to the memory block specified by the block selection signal from the block selector 107 is driven into an active state. The common data bus 112 is arranged along the entire memory blocks 101a to 101d.
The static semiconductor memory device further includes an output buffer 114 for buffering internal read data read on the common data bus 112 for transmission to a data input/output terminal 113 in data reading, and an input buffer 115 activated in data writing for buffering external write data supplied on the data input/output terminal 113, generating internal write data and transmitting the same onto the common data bus 112. The operation is now briefly described.
The X decoder 105 receives and decodes the complementary internal address signal bits supplied from the X address buffer 102, for driving a row (word line) arranged in common for the memory blocks 101a to 101d into a selected state. Thus, the data of the memory cells connected to the selected row are read on the corresponding bit line pairs in the memory blocks 101a to 101d respectively. The Y decoder 106 decodes the complementary internal address signal bits from the Y address buffer 103 and selects a column in each of the memory blocks 101a to 101d. Thus, the selected columns are electrically connected to the corresponding sense amplifiers 110a to 110d and write drivers 111a to 111d in the memory blocks 101a to 110d respectively.
In data reading, only a sense amplifier provided for the selected memory block is driven into an active state in accordance with the block selection signal from the block selector 107, and the remaining sense amplifiers are held in output high-impedance states. When the memory block 101a is specified, for example, the sense amplifier 110a is activated for amplifying the data read on the selected column of the memory block 101a for transmission to the common data bus 112. The output buffer 114 further buffers the internal read data on the common data bus 112 for transmission to the data input/output terminal 113, to generate external read data DQ.
In data writing, a write driver provided for the selected memory block is driven into an active state in accordance with the block selection signal from the block selector 107. The remaining write drivers are held in output high-impedance states. When the memory block 101a is selected, for example, the write driver 111a further amplifies internal write data transmitted from the input buffer 115 onto the common data bus 112 for transmission onto the selected column of the memory block 101a, thereby writing the data in the selected memory cell.
The block selector 107 decodes the complementary address signal bits from the Z address buffer 104 and generates the block selection signal for specifying one of the four memory blocks 101a to 101d.
As shown in FIG. 28, internal (local) data buses (not shown) provided between the memory blocks 101a to 101d and the corresponding sense amplifiers 110a to 110d and write drivers 111a to 111d can be reduced in length by splitting the memory array 100 into the four memory blocks 101a to 101d, whereby loads of the internal data buses are reduced so that the data can be read/written at a high speed. In data reading, further, the data of the selected memory cell can be reliably transmitted onto the internal data bus at a high speed due to the small load thereof.
FIG. 29 more specifically illustrates the structure of the memory array 100 shown in FIG. 28. This figure representatively shows the structure of the two memory blocks 101a and 110d.
Referring to FIG. 29, each of the memory blocks 101a and 101d has the same structure and includes memory cells MC arranged in rows and columns, bit line pairs BLP0 to BLPk arranged in correspondence to the respective columns of the memory cells MC, bit line load circuits LD0 to LDk provided in correspondence to the bit line pairs BLP0 to BLPk respectively for precharging the corresponding bit line pairs BLP0 to BLPk at a prescribed potential and supplying a current to the corresponding bit lines BLP0 to BLPk in data reading, and multiplexers MX0 to MXk provided in correspondence to the bit line pairs BLP0 to BLPk respectively for selectively conducting in response to column selection signals Y0 and /Y0 to Yk and /Yk received from the Y decoder 106 shown in FIG. 28 and electrically connecting the corresponding bit line pairs BLP0 to BLPk to corresponding local data buses IOBa (or IOBd). Each of the bit line pairs BLP0 to BLPk includes bit lines BL and /BL for transmitting complementary data signals.
Each of the bit line load circuits LD0 to LDk includes resistively connected n-channel MOS transistors T0 and T1 provided between a power supply node Vcc and the respective bit lines BL and /BL.
Each of the multiplexers MX0 to MXk comprises CMOS transmission gates provided in correspondence to the bit lines BL and /BL respectively for conducting in response to corresponding complementary column selection signals Yi and /Yi (i=0 to k).
Word lines WL0, WL1, . . . are arranged in common for the respective rows of the memory cells MC forming the memory blocks 101a to 101d. These word lines WL0, WL1, . . . are connected with the memory cells MC arranged in correspondence to the corresponding rows of the memory blocks 101a to 101d respectively. In other words, the word lines WL0, WL1, . . . are arranged in common for the respective rows of the memory blocks 101a to 101d. When any word line is driven into a selected state in accordance with a row selection signal from the X decoder 105 shown in FIG. 28, therefore, a row of memory cells MC are simultaneously driven into selected states in each of the memory blocks 101a to 101d.
The local data buses IOBa to IOBd are provided for only the corresponding memory blocks 101a to 101d respectively. The sense amplifier 110a and the write driver 111a provided for the memory block 101a are enabled when a block selection signal BSa is activated. The sense amplifier 110d and the write driver 111d provided for the memory block 101d are enabled when a block selection signal BSd is activated. The sense amplifiers 110a to 110d receive a sense amplifier activation signal SAE, and the write drivers 111a to 111d receive a write driver enable signal WDE.
These sense amplifiers 110a to 110d are driven into active states when both of the sense amplifier activation signal SAE and the corresponding block selection signals BS (BSa to BSd) are in active states, for amplifying data read from the corresponding memory blocks 101a to 101d to the corresponding local data buses IOBa to IOBd respectively. The write drivers 111a to 111d are activated when both of the corresponding block selection signals BS (BSa to BSd) and the write driver enable signal WDE are in active states, for amplifying data supplied onto the common data bus 112 and transmitting write data to the corresponding local data buses IOBa to IOBd respectively. The operation is now briefly described.
The potential of a selected word line rises in accordance with a word line selection signal from the X decoder 105 shown in FIG. 28. Consider the case of driving the word line WL0 into a selected state. In this state, data stored in the memory cells MC connected with this word line WL0 are read on the corresponding bit line pairs BLP0 to BLPk in the memory blocks 101a to 101d respectively. At this time, a potential difference according to the data stored in each memory cell MC is caused between the bit lines BL and /BL in each of the bit line pairs BLP0 to BLPk due to a supply current (column current) from each of the bit line load circuits LD0 to LDk.
Further, a column is selected in each of the memory blocks 101a to 101d in accordance with the column selection signals Yi and /Yi from the Y decoder 106 shown in FIG. 28. Consider the case of selecting the bit line pairs BLP0. In this case, the multiplexers MX0 conduct to connect the bit line pairs BLP0 to the corresponding local data buses IOBa to IOBd in the memory blocks 101a to 101d respectively. The sense amplifier activation signal SAE is activated in data reading, while the write driver enable signal WDE is activated in data writing. The sense amplifier activation signal SAE and the write driver enable signal WDE are internally generated in accordance with an output enable signal OE and a write enable signal WE externally supplied respectively.
A single memory block is selected in accordance with the block selection signal BS from the block selector 107 (see FIG. 28). Consider that the memory block 101a is selected and the block selection signal BSa is activated. In this state, the sense amplifier 110a is activated in data reading, for amplifying memory cell data read on the local data bus IOBa for transmission onto the common data bus 112. The write driver 111a is activated in data writing, for generating internal write data on the local data bus IOBa in accordance with write data on the common data bus 112 and writing the same in the memory cell MC through the multiplexer MX0.
In the non-selected memory blocks 101b to 101d, the sense amplifiers 110b to 110d and the write drivers 111b to 111d are in output high-impedance states. Thus, data are read from or written in only the memory block 101a specified by the block selection signal BSa from the block selector 107.
As shown in FIG. 29, the lengths of the local data buses IOBa to IOBd provided for the memory blocks 101a to 101d are reduced and load capacitances thereof are reduced since the memory array 100 is split into the plurality of memory blocks 101a to 101d. Thus, memory cell data read in the corresponding memory blocks 101a to 101d are correctly transmitted to the corresponding sense amplifiers 101a to 101d at a high speed, for enabling high-speed data reading. Also in data writing, the write drivers 111a to 111d, which must drive the local data buses IOBa to IOBd having small loads as well as the bit line pairs BLP0 to BLPk through the corresponding multiplexers MX0 to MXk, can drive one of the bit line pairs BLP0 to BLPk corresponding to the selected column to potential levels corresponding to write data in accordance with the write data at a high speed due to the small loads of the local data buses IOBa to IOBd, for enabling high-speed data writing.
FIG. 30 schematically illustrates the structure of a single memory cell MC. Referring to FIG. 30, the memory cell MC includes n-channel MOS transistors Qa and Qb conducting in response to a signal potential on a word line WL for connecting storage nodes SN and /SN to the bit lines BL and /BL respectively, an n-channel MOS transistor Qc connected between the storage node SN and a ground node Vss with its gate connected to the storage node /SN, an n-channel MOS transistor Qd connected between the storage node /SN and the ground node Vss with its gate connected to the storage node SN, and resistive elements Za and Zb for pulling up the storage nodes SN and /SN to a power supply voltage Vcc level respectively. The resistive elements Za and Zb are formed by polysilicon resistances or thin-film transistors. The MOS transistors Qc and Qd form a flip-flop, for latching data of the storage nodes SN and /SN. The operation of the memory cell MC shown in FIG. 30 is now described with reference to FIG. 31.
Consider that the storage nodes SN and /SN hold data of logical high and low levels respectively, as shown in FIG. 31. In this state, the MOS transistors Qc and Qd are in OFF and ON states respectively. The resistive elements Za and Zb have extremely high resistance values, and only a small current flows through the resistive elements Za and Zb.
When the word line WL is selected and its potential increases, the MOS transistors Qa and Qb conduct to electrically connect the storage nodes SN and /SN to the bit lines BL and /BL respectively. The bit lines BL and /BL are supplied with a current from the bit line load circuit LD. The potential of the storage node SN is at a high level, and no current from the bit line load circuit LD flows into the storage node SN and the bit line BL maintains the high level. Because the storage node /SN is at a low level, on the other hand, the current from the bit line load circuit LD flows through the MOS transistors Qb and Qd to reduce the potential of the bit line /BL. The potential of the bit line /BL is set by the ratio of its resistance to the ON resistances of the MOS transistors Qb and Qd. Such potential reduction of the bit line /BL results in a potential difference between the bit lines BL and /BL. The corresponding sense amplifier (any of 110a to 110d) shown in FIG. 29 senses and amplifies the potential difference between the bit lines BL and /BL.
The current, called a column current Ic, flowing from the bit line BL (/BL) to the storage node SN (/SL) storing the low level data flows in all columns in selection of the word line WL. When the word line WL makes a transition to a non-selected state, the storage nodes SN and /SN return to the original potential levels by latch circuits of the MOS transistors Qc and Qd.
In data writing, the word line WL is driven into a selected state similarly to the case of data reading, to cause a potential difference between the bit lines BL and /BL. In this case, the corresponding write driver drives the bit lines BL and /BL into high and low levels respectively in response to the write data, and sets the potentials of the storage nodes SN and /SN at levels corresponding to the write data. Thus, the data is written.
When a word line is driven into a selected state in the conventional static semiconductor memory device, the column current Ic shown in FIG. 31 flows to all memory cells MC connected with the selected word line. If a number of memory cells MC are connected to a single word line, therefore, the total value of the column current Ic is so increased that current consumption is increased and a low current consumptionization cannot be implemented. In order to reduce current consumption by such column current Ic, the number of the memory cells MC connected to a single word line must be reduced. Techniques of reducing the number of memory cells connected to a single word line include a word line driving system called a divided word line structure.
FIG. 32A schematically illustrates the structure of a memory array of the divided word line arrangement. Referring to FIG. 32A, the memory array is divided into four memory blocks a, b, c and d. Global word lines GWL0, GWL1, . . . are arranged in common for respective rows of the memory blocks a to d. A row selection signal from the X decoder 105 shown in FIG. 28 is transmitted to the global word lines GWL0, GWL1, . . .
In each of the memory blocks a to d, local word lines LWL are arranged in correspondence to respective rows of memory cells MC and connected with the memory cells MC of the corresponding rows. Referring to FIG. 32A, local word lines LWLa0, LWLb0, LWLc0 and LWLd0 are arranged in correspondence to the global word line GWL0, and local word lines LWLa1, LWLb1, LWLc1 and LWLd1 are arranged in correspondence to the global word line GWL1 in the memory blocks a to d respectively.
Local decoders LGa0 to LGd0 and LGa1 to LGd1 for receiving signal potentials from the corresponding global word lines GWL0 and GWL1 and memory block selection signals BS (BSa to BSd) are arranged in correspondence to the local word lines LWLa0 to LWLd 0, LWLa1 to LWLd1, . . . These local decoders LGa0 to LGd0, LGa1 to LGd1, . . . drive the corresponding local word lines LWL into selected states when the signal potentials on the corresponding global word lines GWL0, GWL1, . . . are in selected states and the corresponding block selection signals BS (BSa to BSd) are in active states. The block selector 107 shown in FIG. 28 supplies one of the block selection signals BSa to BSd, for specifying one of the memory blocks a to d.
In operation, a single global word line and a single block selection signal are driven into selected states. Consider the case of driving the global word line GWL0 and the block selection signal BSa into selected states. In this case, an output signal from the local decoder LGa0 enters an active state to drive the corresponding local word line LWLa0 into a selected state. Therefore, the column current Ic flows only to the memory cells MC connected to the local word line LWLa0. In the non-selected memory blocks b to d, the local word lines LWLb 0 to LWLd 0 and LWLb1 to LWLd1 are in non-selected states since all block selection signals BSb to BSd are in non-selected states. Therefore, all memory cells MC are in non-selected states and supplied with no column current Ic in the non-selected memory blocks b to d. In the memory block a, the output signal of the local decoder LGa1 is in an inactive state and the local word line LWLa1 maintains a non-selected state even if the block selection signal BSa is driven into a selected state, since the global word line GWL1 is in a non-selected state.
In the divided word line structure shown in FIG. 32A, therefore, the column current Ic flows only in the selected memory block a, and hence current consumption in selection of the memory cells MC can be reduced.
Only a single memory block is driven into a selected state in the divided word line structure, whereby only a single write driver and a single sense amplifier may be provided commonly for all the memory blocks in case of inputting/outputting 1-bit data. In a structure of inputting/outputting multi-bit data, however, a single memory block must be divided in correspondence to the data bits respectively. Namely, a single memory block # (any of a to d) is split into a plurality of subblocks IO0 to IOj as shown in FIG. 32B.
FIG. 32B shows a single global word line GWL and a local word line LWL arranged in correspondence thereto. When the block selection signal BS and the global word line GWL are driven into selected states, the local word line LWL is also driven into a selected state for selecting 1-bit memory cell in each of the subblocks IO0 to IOj. These subblocks IO0 to IOj correspond to data bits DQ0 to Dqj respectively. A column selection signal outputted from the Y decoder 106 shown in FIG. 28 simply selects 1-bit memory cell from each of the subblocks IO0 to IOj.
In case of driving only a single memory block into a selected state for inputting/outputting multi-bit data as shown in FIG. 32B, the following problems arise.
FIG. 33 schematically illustrates the overall structure of a static semiconductor memory device for inputting/outputting a 2-bit word. This static semiconductor memory device includes four memory blocks #0 to #3. Each of the memory blocks #0 to #3 is divided into two subblocks IO0 and IO1 in correspondence to 2-bit data DQ0 and DQ1 respectively. Consider that the memory blocks #0 and #1 share a global word line in the divided word line structure and the memory blocks #2 to #3 share another global word line in the divided word line structure. The global word line is driven into a selected state in the memory blocks #0 and #1 or #2 and #3. The global word lines are arranged in common for the memory blocks #0 and #1 and for the memory blocks #2 and #3 respectively, and local decoders are arranged for respective local word lines to be supplied with block selection signals, thereby implementing block splitting of the divided word line structure.
Each of the memory blocks #0 to #3 is provided with sense amplifiers and write drivers for reading/writing internal data from/in the subblocks IO0 and IO1 respectively. The memory block #0 is provided with a sense amplifier SA00 for receiving a block selection signal BS0 and a sense amplifier activation signal SAE and a write driver WD00 for receiving the block selection signal BS0 and a write driver enable signal WDE for the subblock IO0. The memory block #0 is also provided with a sense amplifier SA01 for receiving the block selection signal BS0 and the sense amplifier activation signal SAE and a write driver WD01 for receiving the block selection signal BS0 and the write driver enable signal WDE for the subblock IO1.
The memory block #1 is provided with a sense amplifier SA10 for receiving a block selection signal BS1 and the sense amplifier activation signal SAE and a write driver WD10 for receiving the block selection signal BS1 and the write driver enable signal WDE for the subblock IO0, and a sense amplifier SA11 for receiving the block selection signal BS1 and the sense amplifier activation signal SAE and a write driver WD11 for receiving the block selection signal BS1 and the write driver enable signal WDE for the subblock IO1.
The memory block #2 is provided with a sense amplifier SA20 for receiving a block selection signal BS2 and the sense amplifier activation signal SAE and a write driver WD20 for receiving the block selection signal BS2 and the write driver enable signal WDE for the subblock IO0, and a sense amplifier SA21 for receiving the block selection signal BS2 and the sense amplifier activation signal SAE and a write driver WD21 for receiving the block selection signal BS1 and the write driver enable signal WDE for the subblock IO1.
The memory block #3 is provided with a sense amplifier SA30 for receiving a block selection signal BS3 and the sense amplifier activation signal SAE and a write driver WD30 for receiving the block selection signal BS3 and the write driver enable signal WDE for the subblock IO0, and a sense amplifier SA31 for receiving the block selection signal BS3 and the sense amplifier activation signal SAE and a write driver WD31 for receiving the block selection signal BS3 and the write driver enable signal WDE for the subblock IO1.
Internal common data buses 120a and 120b are provided in common for the memory blocks #0 to #3. The internal common data bus 120a is connected with the sense amplifiers SA00, SA10, SA20 and SA30 and the write drivers WD00, WD10 WD20 and WD30 provided for the subblocks IO0, and the internal common data bus 120b is connected with the sense amplifiers SA01, SA11, SA21 and SA31 and the write drivers WD01, WD11, WD21 and WD31 provided for the subblocks IO1.
These internal common data buses 120a and 120b are connected with input/output buffers 122a and 122b provided in the vicinity of pads (data input/output nodes) 121a and 121b respectively.
Only a single memory block is driven into a selected state in the structure shown in FIG. 33, so that 1-bit memory cell is selected in each of the two subblocks IO0 and IO1 of the selected memory block and data are transferred to/received from the selected memory cells through the input/output buffers 122a and 122b and the common data buses 120 and 120b.
In the block division structure dividing the memory blocks into the subblocks in correspondence to the data bits respectively, however, the sense amplifiers and the write drivers must be provided in correspondence to the respective data bits, leading to large occupied areas by the sense amplifiers and the write drivers.
The sense amplifiers and the write drivers of the subblocks provided for the same data bits are connected to the same common data bus line 120a or 120b. The sense amplifiers and the write drivers provided for non-selected memory blocks are brought into output high-impedance states, to exert no bad influence on reading/writing of memory cell data for the selected memory block. However, a number of sense amplifiers and write drivers are connected to each internal common data bus, and hence the load capacitance of the bus is so increased that data cannot be transferred at a high speed.
Not only in the divided block structure shown in FIG. 33 but also in the array structure shown in FIG. 28, the block selection signal must be supplied to the sense amplifier or the write driver for controlling activation/inactivation thereof in case of reading/writing data from/in one of a plurality of memory blocks. Thus, the length of an interconnection line for transmitting the block selection signal is increased to increase the occupying area of the interconnection line, and the block selection signal cannot be transmitted at a high speed.
Further, each of the common data buses 120a and 120b is arranged in common for a plurality of memory blocks, and hence its length is increased, the load is increased, an internal data signal cannot be transmitted at a high speed, and high-speed access cannot be implemented. In case of employing such common data buses 120a and 120b, further, output drivability of input buffers included in the input/output buffers 122a and 122b and the sense amplifiers SA00 to SA31 must be increased for driving relatively large loads at a high speed. Thus, excessive loads must be charged/discharged in charging/discharging of signal lines, leading to increase of power consumption.
Particularly in case of increasing the output drivability of output buffers in the input/output buffers 122a and 122b in order to compensate for signal propagation delay in the common data buses 120a and 120b, the input/output pads (data input/output nodes) 121a and 121b are driven at a high speed, leading to ringing resulting from undershoot or overshoot in the input/output pads 121a and 121b. Thus, a long time is required for stably outputting definite data, and the data cannot be read at a high speed.